System Verilog (9) 结构体

module tb;
  struct{
  string fruit;
    int count;
    byte expiry;
  } st_fruit;
  initial begin
    st_fruit = '{"apple",4,15};
    $display("st_fruit=%p",st_fruit);
    st_fruit.fruit="pineapple";
    st_fruit.expiry=7;
    $display("st_fruit=%p",st_fruit);
  end 
endmodule

# Loading sv_std.std
# Loading work.tb(fast)
# 
# vsim -voptargs=+acc=npr
# run -all
# st_fruit='{fruit:"apple", count:4, expiry:15}
# st_fruit='{fruit:"pineapple", count:4, expiry:7}
# exit
# End time: 10:07:53 on Mar 31,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
Done

module tb;
  typedef struct{
    string fruit;
    int count;
    byte expiry;
  } st_fruit;
  initial begin 
    st_fruit fruit1='{"apple",4,15};
    st_fruit fruit2;
    $display("fruit1=%p fruit2=%p",fruit1,fruit2);
    fruit2=fruit1;
    $display("fruit1=%p fruit2=%p",fruit1,fruit2);
    fruit1.fruit="orange";
      $display("fruit1=%p fruit2=%p",fruit1,fruit2);
  end
endmodule

# Loading sv_std.std
# Loading work.tb(fast)
# 
# vsim -voptargs=+acc=npr
# run -all
# fruit1='{fruit:"apple", count:4, expiry:15} fruit2='{fruit:"", count:0, expiry:0}
# fruit1='{fruit:"apple", count:4, expiry:15} fruit2='{fruit:"apple", count:4, expiry:15}
# fruit1='{fruit:"orange", count:4, expiry:15} fruit2='{fruit:"apple", count:4, expiry:15}
# exit
# End time: 22:45:38 on Mar 31,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 1
Done

typedef struct packed{
  bit[3:0] mode;
  bit[2:0] cfg;
  bit en;
} st_ctrl;
module tb;
  st_ctrl ctrl_reg;
  initial begin
    ctrl_reg = '{4'ha, 3'h5, 1};
    $display("ctrl_reg=%p",ctrl_reg);
    ctrl_reg.mode=4'h3;
    $display("ctrl_reg=%p",ctrl_reg);
    ctrl_reg=8'hfa;
    $display("ctrl_reg=%p",ctrl_reg);
  end
endmodule

# Loading sv_std.std
# Loading work.testbench_sv_unit(fast)
# Loading work.tb(fast)
# 
# vsim -voptargs=+acc=npr
# run -all
# ctrl_reg='{mode:10, cfg:5, en:1}
# ctrl_reg='{mode:3, cfg:5, en:1}
# ctrl_reg='{mode:15, cfg:5, en:0}
# exit
# End time: 22:55:44 on Mar 31,2022, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
Done