【分享】给Vivado Block Design的TCL脚本添加IP repository（仓库）路径信息

作者： 付汉杰 hankf@xilinx.com hankf@amd.com
测试环境： Vivado 2021.2
致谢： 同事John Hu提供了命令，非常感谢。

在Vivado里，可以从Block Design导出TCL脚本，保存工程。之后可以从TCL脚本恢复工程。

导出的TCL脚本中，可能不包含用户IP的路径信息。这样的话，从TCL脚本恢复工程时会报告错误。错误信息如下：

INFO: [BD::TCL 103-2011] Checking if the following IPs exist in the project's IP catalog:  
xilinx.com:ip:axi_iic:2.1 xilinx.com:ip:axi_intc:4.1 xilinx.com:ip:axi_noc:1.0 xilinx.com:ip:bufg_gt:1.0 xilinx.com:ip:clk_wizard:1.0 user.org:user:pcie_reg_space:1.1 xilinx.com:ip:proc_sys_reset:5.0 xilinx.com:ip:smartconnect:1.0 xilinx.com:ip:versal_cips:3.1 xilinx.com:ip:xlconcat:2.1 xilinx.com:ip:xlconstant:1.1 xilinx.com:ip:xlslice:1.0 xilinx.com:ip:axis_subset_converter:1.1 xilinx.com:ip:axis_switch:1.1 xilinx.com:ip:mipi_csi2_rx_subsystem:5.1 xilinx.com:ip:v_demosaic:1.1 xilinx.com:ip:v_frmbuf_wr:2.3 xilinx.com:ip:v_proc_ss:2.3 xilinx.com:ip:axis_register_slice:1.1 xilinx.com:ip:gt_quad_base:1.1 xilinx.com:ip:hdmi_gt_controller:1.0 xilinx.com:ip:util_ds_buf:2.2 xilinx.com:ip:v_hdmi_tx_ss:3.2 xilinx.com:ip:v_mix:5.2  .
WARNING: [Coretcl 2-175] No Catalog IPs found
ERROR: [BD::TCL 103-2012] The following IPs are not found in the IP Catalog:
  user.org:user:pcie_reg_space:1.1

Resolution: Please add the repository containing the IP(s) to the project.
# if { $bCheckIPsPassed != 1 } {
#   common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
#   return 3
# }
WARNING: [BD::TCL 103-2023] Will not continue with creation of design due to the error(s) above.

update_compile_order -fileset sources_1

在TCL文件中添加下列命令，可以添加IP repository（仓库），使Vivado找到IP。添加的位置，可以是创建工程（create_project）之后，创建Block Design（create_bd_design）之前。

# Specify and refresh the IP local repo
set_property ip_repo_paths "$script_folder/ipdefs/ip" [current_project]
update_ip_catalog

其中“$script_folder”是指当前TCL脚本所在的目录。目录"$script_folder/ipdefs/ip"下，每个IP应该有一个目录，IP目录下有文件component.xml。

从头开始的部分TCL脚本内如如下：

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project mipi_layout mipi_layout_vivado -part xcvc1902-vsva2197-2MP-e-S
   set_property BOARD_PART xilinx.com:vck190:part0:2.2 [current_project]
}

# CHANGE DESIGN NAME HERE
variable design_name
set design_name mipi

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

# Specify and refresh the IP local repo
set_property ip_repo_paths "$script_folder/dapd.ipdefs/ip" [current_project]
update_ip_catalog