设计一个4位二进制计数器
Function:Four bit binary counter
1.design code
module top_module ( input clk, input reset, // Synchronous active-high reset output reg [3:0] q); always @(posedge clk) begin if (reset) begin q <= 4'd0; end else begin q <= q + 1'b1; end end endmodule
2.testbench code
module top_module_testbench(); reg clk; reg reset; wire [3:0] q; top_module instance1( .clk(clk), .reset(reset), .q(q) ); initial begin #0 clk = 0; reset = 0; #4 reset = 1; #12 reset = 0; #400 $stop; end always #5 clk = ~clk; endmodule