UVM DPI

refer to this link: https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.2/html/index.html

 Verilog提供VPI用来和C/C++通信，如果只是单纯地使用VPI进行后门访问操作，那么在SystemVerilog中进行后门访问就很麻烦，因为必须先将SystemVerilog的访问转换称C/C++的访问。而SystemVerilog提供DPI用来和C/C++通信，因此UVM提供了上述方法架构，将SystemVerilog和C/C++的后门访问统一起来。

具体方法如下：

• uvm_hdl_check_path("tb.top_env.dmac.channel.chn_ctrl.fifo_status");
• Checks that the given HDL path exists. Returns 0 if NOT found, 1 otherwise.

• uvm_hdl_deposit("tb.top_env.dmac.channel.chn_ctrl.fifo_status", 'h1); 
• Sets the given HDL path to the specified value. Returns 1 if the call succeeded, 0 otherwise.

• uvm_hdl_force("tb.top_env.dmac.channel.chn_ctrl.fifo_status", 'h1);  
• Forces the value on the given path. Returns 1 if the call succeeded, 0 otherwise.

• uvm_hdl_force_time("tb.top_env.dmac.channel.chn_ctrl.fifo_status", 'h1, 100);
• Forces the value on the given path for the specified amount of force_time. If force_time is 0, uvm_hdl_deposit is called. Returns 1 if the call succeeded, 0 otherwise. 

• uvm_hdl_release_and_read("tb.top_env.dmac.channel.chn_ctrl.fifo_status", 'h0);  
• Releases a value previously set with uvm_hdl_force. Returns 1 if the call succeeded, 0 otherwise.  value is set to the HDL value after the release. For ‘reg’, the value will still be the forced value until it has been procedurally reassigned. For ‘wire’, the value will change immediately to the resolved value of its continuous drivers, if any. If none, its value remains as forced until the next direct assignment.

• uvm_hdl_release("tb.top_env.dmac.channel.chn_ctrl.fifo_status");  
• Releases a value previously set with uvm_hdl_force. Returns 1 if the call succeeded, 0 otherwise.

• uvm_hdl_read("tb.top_env.dmac.channel.chn_ctrl.fifo_status", rd_value); 
• Gets the value at the given path. Returns 1 if the call succeeded, 0 otherwise.